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Actel License For Libero

We offer multiple licenses to design with our FPGA and SoC design tools. Most of the software tools and FPGA IP cores are freely available but a few high-value IP cores and resources needed to work with high-density FPGAs required paid licenses.

Actel License For Libero


Now available for free with all versions of Libero 6.0, Synplicity's Synplify AE software includes Synplicity's SCOPE Editor, which allows users to add timing and other constraints through a GUI. In addition, Actel Libero Silver and Gold users now have access to other features not previously enjoyed, such as the Hierarchical Netlist Browser, batch or command line mode (for floating licenses), and interface to the HDL Analyst.

Libero 6.0 IDE is available in three editions: Platinum, Gold and Silver. Libero Platinum is a complete solution with unlimited design capacity and customer support and is priced at $2495. For users designing system-level devices of 300k gates or less, Actel offers its Libero Gold edition, which is priced at $595. The Libero Silver edition may be used free of charge via Actel's Web site. The Synplify Pro AE add-on, which can be used with any Libero or Designer edition, is priced at $3500 annually and requires a separate license. For more information, please contact Actel.

Libero offers four levels of licenses: Evaluation, Silver, Gold, and Platinum. These licenses differ in price, device support, and length of service. The licenses most often requested by the first-time Libero users are the two time-limited, no-cost licenses: Evaluation and Silver.

In the installer answer the questions and set a path to extract the files to, e.g. /home/user/programs/microsemi/libero/v12.1/ and /home/user/programs/microsemi/common.There is a graphical installer available, just replace console with gui in the call above.

Furthermore the outdated libz version shipped by Microsemi does not work with the repository version of lib32-libpng12.In /home/user/programs/microsemi/libero/v12.1/Libero/lib do the following to make Libero use your library installed by pacman:

The $LD_LIBRARY_PATH has to include the libraries from the 32-bit Qt installation, $LM_LICENSE_FILE reflects your Libero license server on which the license daemon runs on some port under some url domain.of.your.license.server. $SNPSLMD_LICENSE_FILE is needed for the Synopsys tools used in Libero, set this to a different server and port if you have multiple license daemons running or to $LD_LIBRARY_PATH if not.

A application menu entry (which a lot of desktop environments and window managers follow) can be added to the system by creating a libero.desktop file in your /.local/share/applications directory:

Some may add that to the startup-script to apply it on start.The install and vault locations have to be set on installation or may be edited in /home/user/programs/microsemi/libero/v12.1/Libero/data/install.def when moving the files afterwards.

Check the SERVER line of the license file (in the above example, 0128D07E321F) to verify it is correct. Compare the hostid with the hostid in your previous license file. Or, run the lmhostid command to ensure that the hostid matches.

Do not change the hostid. If you change the hostid, you will invalidate your license key file.If the hostid is incorrect, contact your account manager to request a new license key file.

Add the path to any license option file(s) after the vendor daemon path. For example,VENDOR snpslmd /synopsys/scl/2022.12/linux64/bin/snpslmd \/synopsys/scl/2022.12/linux64/bin/snpslmd.opt

For each user account that will be running the Synopsys tools, set a licensing environment variable.The licensing variable is a pointer that tells the Synopsys tools where to find the license file.

Altium Designer (from build 10.1327.26514 onwards) supports Altera Nios II 5.1 to 12.0 (SP2) which is available in Nios II Embedded Design Suite 5.1 to 12.0 (SP2). Note: A valid full license of Altera Nios II is required to successfully use the Nios II core.

Altium Designer (from build onwards) supports Xilinx MicroBlaze 4.00 and 6.00 which is available in EDK 7.1 to 8.1 and EDK 8.2 to 10.1 respectively. Note: A valid full license of Xilinx EDK is required to successfully use the MicroBlaze core.

Pricing and Availability Actel's Core AI will be available for free in April. Also free, the CoreConsole 1.1 IDP and Libero 7.1 IDE Gold will be available in April for download via Actel's Web site. A Platinum edition of Libero 7.1 IDE is available for $2495. All editions are one-year renewable licenses.The M7AFS family includes four devices of varying gate densities, levels of embedded flash and analog channels. Samples of the M7AFS600 device will be available in April, with the M7AFS1500 sampling in 2H 2006. Implementation of CoreMP7 in Actel's ARM7-enabled Fusion devices starts below $5 in 250K-unit volumes.

Fusion and CoreMP7 The first mixed-signal FPGA supports between 600K and 1.5 million system gates; 13.5 to 33.7-KBytes of SRAM; 512-KByte to 1-Mbyte of flash; analog inputs of &plumn;12-V; and a 12-bit analog-to-digital converter with up to 600KSPS. The CoreMP7 is the industry's only soft 32-bit ARM7 core for FPGAs, and is user programmed to FPGAs. It is optimized in size and speed for the M7 Fusion products, and doesn't require an ARM7 license or royalty fee.

CoreConsole IDP v1.1 supports ARM7-enabled M7AFS devices, offers full AHB multi-master support, and includes a memory map generation with software driver export. It has a new scalable user interface and is available for free download at Libero Gold includes support for up to one million gates for free as well. Libero IDE 7.1 features Fusion SmartGen, which enables the configuration of analog capabilities.

When using EDA tools for digital development, first of all, the functional requirements of system development concepts and original development specifications should be transformed into format files that can be recognised by subsequent development tools, such as synthesis tools, simulation tools and layout and wiring tools. The developed function definition shall first be converted into standard circuit diagram form and standard language description form. Then the conversion from language level to gate level circuit was completed. After the synthesis was completed, there was no error. Then, layout and wiring were carried out, and the programme file was downloaded, as shown in Figure 11. Actel FPGA development environment libero needs multiple software support and requires different software to complete corresponding functions in each stage. The simulation is called ModeSim, the synthesis is called Synplify, the layout and wiring is called Designer, the download is called the FlashPro tool and so on.


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